Tech giants join forces for faster server tech

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Tech giants join forces for faster server tech

OpenCAPI to provide ten-fold performance boost.

Google and a group of IT hardware companies have joined forces to develop the open coherent accelerator processor interface (OpenCAPI) specification, providing a foundation for high-speed microprocessor interconnect systems to devices.

The open interface architecture is based on IBM's CAPI for POWER8 processors. OpenCAPI will however be processor design-agnostic. 

The idea is to allow fast, direct connections between applications and user-level hardware accelerators and advanced memory systems for cloud servers and big data and analytics.

OpenCAPI does away with the need to run device drivers and communication with accelerators over a bus like PCIe, which adds latency and slows performance.

Hardware acceleration will become more commonplace thanks to microprocessor technology no longer delivering the historical cost/performance improvement for each new generation, OpenCAPI's founding board - consisting of AMD, IBM, Google, Mellanox and Micron - said in a technology overview [pdf].

The initiative has also attracted Hewlett Packard Enterprise, Nvidia, and Xilinix as contributors, while Dell-EMC has joined as an observer.

The world's largest microprocessor maker, Intel, is not part of the OpenCAPI consortium and is not expected join.

"As artificial intelligence, machine learning and advanced analytics become the price of doing business in today's digital era, huge volumes of data are now the norm," Doug Balog, general manager for IBM Power, told Reuters.

"It's clear that today's datacenters can no longer rely on one company alone to drive innovation."

IBM will feature OpenCAPI in its POWER9 products due out next year, the company's research fellow Brad McCredie said.

OpenCAPI will feature 25 gigabit per second signalling and a protocol that enables a very low latency interface between processors and attached devices.

The consortium intends to deliver the OpenCAPI 3.0 specification and an interface reference design for field-programmable gate array accelerators by mid-2017.

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