Intel sets sail for HPC standardisation

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Intel sets sail for HPC standardisation

Cluster Ready platform promises better hardware/software interoperability.

Intel is hoping that a new standard will tighten the bond between different high performance computing (HPC) clusters. 

The chipmaker is scheduled to launch the new Cluster Ready platform definition at the International Supercomputing Conference in Dresden today.

The initiative will set standards for hardware clusters and provide software certification programming, allowing users to verify that hardware and software interoperate without requiring any testing.

A new cluster validation tool will allow users to verify that their hardware meets the standard's specifications and confirm that the cluster is operational before third-party applications are loaded. It will also enable diagnostic services to track errors.

Systems qualifying for the programme require an Intel processor. Early backers of the standard include Dell, Platform Computing and SGI.

Compute clusters currently dominate the HPC segment. Combining dozens, and in some cases hundreds, of low cost servers into a large system is generally far cheaper than integrated supercomputers such as mainframe systems that can cost millions of dollars.

Intel is also preparing to unveil a new optical cable to connect the different systems in a cluster that replaces current generation copper cables.

The new Intel Connects Cable offers 20Gbps of throughput over a distance of up to 100 metres.

The cables also cut down on error rates, and offer a claimed latency of no more than 550 picoseconds. A 10-metre cable will be priced at the same range as a copper cable.

Current generation copper cables bridge no more than 10 metres, which restricts the size of compute clusters. Intel suggested that the cable will allow for far larger clusters that contain thousands of systems spread out over multiple floors.

Firms could also opt to organise their HPC systems in a different way, for instance by grouping all storage, processors and switches in separate spaces.
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