This hybrid structure may be more reliable than other recently built nanowire-based memory devices and more easily integrated into commercial applications.
The architecture was developed by researchers from the National Institute of Standards and Technology (Nist), George Mason University and Kwangwoon University in Korea.
The technique involves the integration of nanowires with a high-end type of non-volatile memory similar to Flash, a layered structure known as semiconductor-oxide-nitride-oxide-semiconductor technology.
The nanowires are positioned using 'hands-off self-alignment', which could allow the production cost, and therefore the overall cost, of large-scale viable devices to be lower than Flash memory cards, which require more complicated fabrication methods.
Researchers grew the nanowires on a layered oxide-nitride-oxide substrate. Applying a positive voltage across the wires causes electrons in the wires to tunnel down into the substrate thereby charging it.
A negative voltage causes the electrons to tunnel back up into the wires. This process is the key to the device's memory function.
When fully charged, each nanowire device stores a single bit of information, either a '0' or a '1' depending on the position of the electrons, the scientists explained.
Two advantages the Nist design may have over alternative proposals for nanowire-based memory devices are better stability at higher temperatures and easier integration into existing chip fabrication technology.
Boffins fire up nanowire memory architecture
By Robert Jaques on Jun 12, 2007 1:04PM