IBM plunges into water-cooled chips

The processors operate with multiple layers of circuits and components stacked on top of each other, allowing for a '3D' design rather than laying all components side by side.

IBM unveiled the technology last year, estimating that it would allow chip designers to boost the number of data transfer channels by a factor of 100 and dramatically reduce the amount of space needed by data to travel between components.

However, heat dissipation becomes a major concern as the components are stacked on each other.

"As we package chips on top of each other to significantly speed a processor's capability to process data, conventional coolers attached to the back of a chip do not scale," said Thomas Brunschwiler, a project leader at IBM's Zurich research lab.

"In order to exploit the potential of high-performance 3D chip stacking, we need interlayer cooling."

To solve the problem, researchers constructed a series of cooling channels which run water between the individual layers through structures as thin as a human hair.

The result is a cooling system capable of providing up to 180W of cooling per square centimetre on each layer.

"This truly constitutes a breakthrough," said Bruno Michel, manager of chip cooling research at the Zurich lab.

"With classic backside cooling, the stacking of two or more high-power density logic layers would be impossible."

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