Intel divulges Nehalem details

Intel has disclosed more details on its forthcoming Nehalem architecture, which is expected to appear in production processors before the end of 2008.

In a paper submitted at the 2008 VLSI Symposia, the chipmaker outlined how Nehalem chips will have their processor cores, memory and I/O decoupled from each other and that each will be able to dynamically shift frequency as necessary to maximise power efficiency.

Nehalem will be "the biggest platform architecture change in a decade," according to Rajesh Kumar, director of Circuit and Low Power Technologies for Intel's Digital Enterprise Group.

The architecture specifies a modular design that scales from two to eight cores to target everything from laptops to desktops to servers.

"We're trying to emphasise energy efficiency for some cases, but high performance for others, so there's a need to be scalable," said Kumar. Because of this, the main components will work in a decoupled mode where the frequency and voltage of each can be set separately.

"So the CPU core can run at its own frequency and voltage, the memory system on its own and the I/O on its own," said Kumar.

Intel also disclosed that Nehalem's QuickPath (QPI) will be capable of moving data between processor sockets at 25GB/s, while each chip has its own memory bus with a bandwidth of 32GB/s.

QPI is Intel's point-to-point interconnect for linking processor chips together and to the rest of the system. AMD already uses similar technology called HyperTransport in its Opteron chips.

Kumar claimed that QPI will be "three times faster than the best competition today," but AMD has recently introduced Opteron chips supporting HyperTransport 3.0, which is capable of 20.8GB/s.

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