Intel is promising a 20 to 45 percent performance improvement for its upcoming processors that are due out later this year, followed by an additional performance boost in 2008 when the chip maker starts shipping its Nehalem micro architecture.
"We view Nehalem as the first truly dynamically scalable micro architecture," Pat Gelsinger, general manager of Intel's Digital Enterprise Group, said at a meeting with reporters in San Francisco.
Intel develops new core architectures on 2-year schedule. The chipmaker's current series was released in March 2006.
"The Core micro architecture is built for 45nm and 65nm," Gelsinger said. " In the case of Nehelam, it's natively architected to take full advantage of 45nm. In that sense it is really going to unlock the full potential of that technology's capabilities, beyond what the Penryn was capable of doing."
Nehalem will introduce two processing threads for each core, up from the current single threaded cores. Intel said it is currently working on 8-core processors, but might introduce larger chips in the future.
Mimicking the way that AMD processors are designed, Nehalem will embed the memory controller onto the chip. It is currently part of the front side bus. In another move that follows AMD's lead, Nehalem will deliver an integrated graphics processor.
Intel didnt' comment on whether the GPU is integrated in the chip package or part of the die. The last option offers better performance and energy consumption, but could result in lower yields during chip manufacturing because it increases the die size.
Nehalem chips won't offer all of the available features, cautioned Gelsinger. It is therefore unlikely that an 8-core processor will come with the integrated graphics processor.
The Nehalem micro architecture is scheduled to start shipping in 2008. Intel later this year plans to release its first 45nm chips codenamed Penrym.
The chipmaker has previously said that Penryn will come in two and four core versions. Gelsinger unveiled additional improvements to the Core micro architecture that will boost performance while cutting power consumption.
The new chip will offer on-chip caches of 12MB for a quad core chip and 6MB for a dual core model. Current dual core chips feature a 4MB cache. The larger memory size will boost performance for certain applications and enable a new power saving feature dubbed 'Deep power down', in which all clocks and caches are powered down completely and the data the they contain is temporarily stored to a special location on the chip's die.
The chip also introduces enhancements to the on-chip virtualization technology that cuts the time that it take to get into and out of an virtual machine by 25 to 75 percent, Gelsinger said.
An updated Dynamic Acceleration Technology furthermore promises to advance non-threaded applications into the multithreaded age.
Software developers have to specially design their software to run on multi-core and multi threaded processors by allowing calculations to be divided between multiple threads or cores. Most of today's consumer desktop applications lack such features. The Penryn processor however will notice when one core is fully used while another is sitting idle, and will move part of the workload to the unused core.
The performance gains between upcoming Penryn systems and current generation 65nm chips depend on the application. Early tests demonstrated at least a 20 per cent improvement, said Gelsinger.
The new SSE4 instruction set allows multi media applications to perform more than 40 per cent better. Increases in the cache sizes and a faster front side bus meanwhile primarily benefit high performance computing and floating point applications, leading to 45 percent performance boosts.
Intel fires up Penryn and Nehalem enhancements
By Tom Sanders on Mar 29, 2007 11:50AM