Boffins unveil trillion calculations per second chip

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Boffins unveil trillion calculations per second chip

Tera-op Reliable Intelligently adaptive Processing System.

US boffins have unveiled a prototype for a revolutionary new general-purpose processor which they claim has the potential to clock up trillions of calculations per second.

The Tera-op Reliable Intelligently adaptive Processing System (Trips) was designed and built by a team of computer scientists at the University of Texas at Austin.

Professors Stephen Keckler, Doug Burger and Kathryn McKinley have been working on the underlying technology that culminated in the Trips prototype for seven years.

The research team designed and built the hardware prototype chips and the software that runs on the chips.

"The Trips prototype is the first on a roadmap that will lead to ultra-powerful, flexible processors implemented in nanoscale technologies," said Burger, associate professor of computer sciences at the University of Texas.

He explained that Trips is a new class of processing architecture called Explicit Data Graph Execution which, unlike conventional architectures that process one instruction at a time, can process large blocks of information all at once and more efficiently.

Current 'multi-core' processing technologies increase speed by adding more processors, which individually may not be any faster than previous processors.

Adding processors shifts the burden of obtaining better performance to software programmers, who must assume the difficult task of rewriting their code to run well on a potentially large number of processors.

"Explicit Data Graph Execution technology offers an alternative approach when the race to multi-core runs out of steam," said Keckler, associate professor of computer sciences.

Each Trips chip contains two processing cores, each of which can issue 16 operations per cycle with up to 1,024 instructions in flight simultaneously.

Current high-performance processors are typically designed to sustain a maximum execution rate of four operations per cycle.

The prototype contains two 16-wide processors per chip, but the research team aims to scale this up with further development.
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