AMD goes low power for quad-core

AMD is preparing a new micro-architecture for its quad-core processors codenamed 'Barcelona' that promise to further cut power consumption, the company revealed at the International Solid State Circuits Conference in San Francisco. 

A micro-architecture is the design on a chip that allows software to interact with the chip architecture. It sits one layer below the instruction set architecture such as the IA-32 that is used in today's AMD Opteron and Intel Xeon processors.

AMD is updating its PowerNow energy management technology for the server chip, allowing each processing core to dynamically adjust frequencies for each individual core depending on compute demands.

The chip also is able to maintain power to the memory controller while cutting down the power on the processor, potentially allowing for additional energy savings.

'Clock gating' technology will allow the chip to shut down certain areas of the processor that are not being used.

While the power management improvements allow the chip to run at cooler temperatures, AMD also promised that the processors will provide a performance boost.

The company claimed that the addition of its L3 cache would increase performance for applications such as web hosting, databases and email servers.

The improvements will allow the chip to outpace Intel's quad-core processors by 40 per cent on average, according to AMD.

Intel is currently ahead of AMD in the race for the raw performance of its chips. But AMD is generally expected to take back the lead when it launches its quad-core processors.

Intel's quad-core chip bundles two dual-core dies in a single package, each with its own cache memory.

When data has to travel from the first core to the fourth, or when one core has to pull information from the cache memory on the other chip, the information has to travel a relatively long distance, causing a jump in power consumption and a drop in chip performance.

AMD's chips, by contrast, feature a monolithic design where all cores and cache memory are bundled on one physical chip.

The Barcelona chip is slated for availability in mid-2007.

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