MIT 'nanoruler' to yield next-gen computer chips

The tool, called the nanoruler, improves currently-used nanoscale lithographic technology for accurately etching fine patterns of lines on tiny surfaces.

Announced last week, the technique is expected to enable the low cost, high yield production of nanoscale devices, making possible the commercialization of a wider range of nanotechnology inventions.

“The patterns we made form a regular, very dense and very precise grating pattern,” said Ralf Heilmann, who developed the nanoruler with a team of researchers at the MIT Kavli Institute of Astrophysics and Space Research.

“It [the pattern] could serve as a grid or registration pattern for building functional circuits. The higher grid density might allow more densely packed circuits and thus more powerful processors.”

“Our technique might also find application in the fabrication of photonic crystals and other high-precision 2-D and 3-D structures,” he said.

Using the nanoruler, the researchers created lines about 25 nanometres (nm) wide that separated by 25nm spaces -- 60 percent smaller than the patterns on current commercially available computer chips.

Patterns were created using a high-precision variant of interference lithography, called scanning-beam interference lithography.

While current techniques rely on 193nm ultraviolet light, the MIT technique creates interference patterns using laser light with a wavelength of 351nm that is controlled by custom high-speed electronics.

The researchers expect 25nm features to reach the industry in the 2013-2015 timeframe, with Intel’s recent announcement of 32nm processors by 2009.

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